Follow-up to #346 / SCHED_MIC (#385).
SCHED_MIC orders Intel cores P -> E -> P SMT sibling -> LP, but there is no sysctl to make E cores top priority over P (the laptop "favor battery" use case from #346). Only the AMD cache/compute swap exists (kern.sched.prefer_compute).
Goal: add a knob (e.g. kern.sched.prefer_efficiency) that swaps the class-1/class-2 preference on Intel hybrid parts, analogous to prefer_compute for AMD, leaving the rest of the ordering intact. Update sched_mic(4).
Relevant code: sched_class_cost() / sched_prefer_compute handling in sys/kern/sched_mic.c.
Follow-up to #346 / SCHED_MIC (#385).
SCHED_MIC orders Intel cores P -> E -> P SMT sibling -> LP, but there is no sysctl to make E cores top priority over P (the laptop "favor battery" use case from #346). Only the AMD cache/compute swap exists (
kern.sched.prefer_compute).Goal: add a knob (e.g.
kern.sched.prefer_efficiency) that swaps the class-1/class-2 preference on Intel hybrid parts, analogous toprefer_computefor AMD, leaving the rest of the ordering intact. Updatesched_mic(4).Relevant code:
sched_class_cost()/sched_prefer_computehandling insys/kern/sched_mic.c.