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[JitDiff X64] [BoyBaykiller] JIT: Transform arithmetic using distributive pr ... #2058

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[JitDiff X64] [BoyBaykiller] JIT: Transform arithmetic using distributive pr ...#2058

Description

@MihuBot
MihuBot
opened on Jul 1, 2026

Job completed in 23 minutes 59 seconds (remote runner delay: 1 minute 13 seconds).
dotnet/runtime#126852
Using arguments: -nuget
Main commit: dotnet/runtime@7c4e032
PR commit: BoyBaykiller/runtime@ef82e04

Warning

2 extra test assemblies failed to produce JIT diffs and were excluded from the diff analysis:

  • MathNet.Numerics.dll (pr)
  • Pipelines.Sockets.Unofficial.dll (pr)

All failures happened only on the PR branch, which likely indicates a bug introduced by the PR (e.g. a JIT assert or crash while compiling these assemblies).

Relevant output 
[pr MathNet.Numerics] Error running /ramdisk/artifacts-pr_15/corerun on /ramdisk/extra-projects/MathNet.Numerics/MathNet.Numerics.dll
[pr MathNet.Numerics] 1 errors compiling set.
[pr MathNet.Numerics] Dasm command "jit-dasm-pmi --platform artifacts-pr_15 --cctors --corerun artifacts-pr_15/corerun --jit clr-checked-pr/libclrjit.so --nocopy --output jit-diffs/frameworks/pr/dasmset_94/base /ramdisk/extra-projects/MathNet.Numerics/MathNet.Numerics.dll" returned with 1 failures
[pr MathNet.Numerics] Dasm commands returned 1 base failures, 0 diff failures.
[pr MathNet.Numerics] Warning: Failures detected generating asm: 1 base, 0 diff
[pr Pipelines.Sockets.Unofficial] Error running /ramdisk/artifacts-pr_7/corerun on /ramdisk/extra-projects/Pipelines.Sockets.Unofficial/Pipelines.Sockets.Unofficial.dll
[pr Pipelines.Sockets.Unofficial] 1 errors compiling set.
[pr Pipelines.Sockets.Unofficial] Dasm command "jit-dasm-pmi --platform artifacts-pr_7 --cctors --corerun artifacts-pr_7/corerun --jit clr-checked-pr/libclrjit.so --nocopy --output jit-diffs/frameworks/pr/dasmset_293/base /ramdisk/extra-projects/Pipelines.Sockets.Unofficial/Pipelines.Sockets.Unofficial.dll" returned with 1 failures
[pr Pipelines.Sockets.Unofficial] Dasm commands returned 1 base failures, 0 diff failures.
[pr Pipelines.Sockets.Unofficial] Warning: Failures detected generating asm: 1 base, 0 diff

Diffs

Diffs 
Found 120 files with textual diffs.

Summary of Code Size diffs:
(Lower is better)

Total bytes of base: 389380493
Total bytes of diff: 389379243
Total bytes of delta: -1250 (-0.00 % of base)
Total relative delta: -3.50
    diff is an improvement.
    relative diff is an improvement.


Top file improvements (bytes):
        -371 : BouncyCastle.Cryptography.dasm (-0.01 % of base)
        -371 : BouncyCastle.Crypto.dasm (-0.01 % of base)
        -189 : System.Net.Security.dasm (-0.08 % of base)
         -88 : MailKit.dasm (-0.01 % of base)
         -51 : Microsoft.CodeAnalysis.CSharp.Features.dasm (-0.00 % of base)
         -31 : System.Private.CoreLib.dasm (-0.00 % of base)
         -19 : System.Private.Uri.dasm (-0.02 % of base)
         -18 : Microsoft.CodeAnalysis.Features.dasm (-0.00 % of base)
         -18 : Iced.dasm (-0.00 % of base)
         -17 : StackExchange.Redis.dasm (-0.00 % of base)
         -16 : Microsoft.CodeAnalysis.AnalyzerUtilities.dasm (-0.00 % of base)
         -10 : NuGet.Protocol.dasm (-0.00 % of base)
         -10 : System.Security.Claims.dasm (-0.04 % of base)
         -10 : System.IO.Pipelines.dasm (-0.01 % of base)
         -10 : System.Runtime.InteropServices.dasm (-0.04 % of base)
          -9 : System.Private.Xml.dasm (-0.00 % of base)
          -6 : System.Reflection.Emit.dasm (-0.00 % of base)
          -6 : NetTopologySuite.dasm (-0.00 % of base)

18 total files with Code Size differences (18 improved, 0 regressed), 740 unchanged.

Top method improvements (bytes):
        -185 (-10.09 % of base) : System.Net.Security.dasm - System.Net.Security.MD4:MD4Transform(System.Span`1[uint],System.ReadOnlySpan`1[byte]) (FullOpts)
        -136 (-7.68 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.LongDigest:ProcessBlock():this (FullOpts)
        -136 (-7.68 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.LongDigest:ProcessBlock():this (FullOpts)
         -87 (-5.75 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.Sha224Digest:ProcessBlock():this (FullOpts)
         -87 (-5.75 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.Sha224Digest:ProcessBlock():this (FullOpts)
         -84 (-3.19 % of base) : MailKit.dasm - MailKit.Security.Ntlm.MD4:MD4Transform(byte[],int):this (FullOpts)
         -80 (-3.31 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.MD4Digest:ProcessBlock():this (FullOpts)
         -80 (-3.31 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.MD4Digest:ProcessBlock():this (FullOpts)
         -52 (-2.00 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.Sha1Digest:ProcessBlock():this (FullOpts)
         -52 (-2.00 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.Sha1Digest:ProcessBlock():this (FullOpts)
         -44 (-7.71 % of base) : Microsoft.CodeAnalysis.CSharp.Features.dasm - Microsoft.CodeAnalysis.CSharp.Completion.Providers.DeclarationName.NameDeclarationInfo:GetPossibleMemberDeclarations(Microsoft.CodeAnalysis.Editing.DeclarationModifiers):System.Collections.Immutable.ImmutableArray`1[Microsoft.CodeAnalysis.Diagnostics.Analyzers.NamingStyles.SymbolSpecification+SymbolKindOrTypeKind] (FullOpts)
         -19 (-1.16 % of base) : System.Private.Uri.dasm - System.Uri:ParseRemaining():this (FullOpts)
         -18 (-0.08 % of base) : Iced.dasm - Iced.Intel.InstructionInfoFactory:AddImpliedAccesses(int,byref,uint):this (FullOpts)
         -18 (-4.26 % of base) : Microsoft.CodeAnalysis.Features.dasm - Microsoft.CodeAnalysis.EditAndContinue.AbstractEditAndContinueAnalyzer:AllowsDeletion(Microsoft.CodeAnalysis.ISymbol):bool (FullOpts)
         -16 (-3.46 % of base) : Microsoft.CodeAnalysis.AnalyzerUtilities.dasm - Microsoft.CodeAnalysis.FlowAnalysis.DataFlow.PointsToAnalysis.PointsToAnalysis+PointsToDataFlowOperationVisitor:<SetValueForNullCompareFromPredicate>g__SetAbstractValueFromPredicate|46_0(Microsoft.CodeAnalysis.FlowAnalysis.DataFlow.AnalysisEntity,int,Microsoft.CodeAnalysis.ITypeSymbol,Microsoft.CodeAnalysis.FlowAnalysis.DataFlow.PointsToAnalysis.DefaultPointsToValueGenerator,Microsoft.CodeAnalysis.Compilation,Microsoft.CodeAnalysis.FlowAnalysis.DataFlow.PointsToAnalysis.PointsToAnalysisData,Microsoft.CodeAnalysis.FlowAnalysis.DataFlow.PointsToAnalysis.PointsToAnalysisData) (FullOpts)
         -13 (-2.84 % of base) : System.Private.CoreLib.dasm - System.Sha1ForNonSecretPurposes:Drain(System.Span`1[uint]) (FullOpts)
         -10 (-4.90 % of base) : NuGet.Protocol.dasm - NuGet.Protocol.Plugins.PluginDiscoverer:IsValidPluginFile(System.IO.FileInfo):bool (FullOpts)
         -10 (-0.62 % of base) : System.IO.Pipelines.dasm - System.IO.Pipelines.PipeReader+<ReadAtLeastAsyncCore>d__4:MoveNext():this (FullOpts)
         -10 (-5.10 % of base) : System.Runtime.InteropServices.dasm - System.Runtime.InteropServices.Marshalling.StrategyBasedComWrappers:CreateObject(nint,int):System.Object:this (FullOpts)
         -10 (-0.96 % of base) : System.Security.Claims.dasm - System.Security.Claims.Claim:WriteTo(System.IO.BinaryWriter,byte[]):this (FullOpts)
          -9 (-9.09 % of base) : StackExchange.Redis.dasm - StackExchange.Redis.RedisDatabase+IncrexMessageBase:get_ArgCount():int:this (FullOpts)
          -9 (-1.87 % of base) : System.Private.Xml.dasm - System.Xml.Schema.XmlSchemaValidator:.ctor(System.Xml.XmlNameTable,System.Xml.Schema.XmlSchemaSet,System.Xml.IXmlNamespaceResolver,int):this (FullOpts)
          -8 (-10.96 % of base) : StackExchange.Redis.dasm - StackExchange.Redis.RedisDatabase:ValidateStringIncrementExpiry(StackExchange.Redis.Expiration) (FullOpts)
          -8 (-3.21 % of base) : System.Private.CoreLib.dasm - System.Runtime.CompilerServices.AsyncStateMachineDispatcherInfo:CreateDispatcher(System.Runtime.CompilerServices.IAsyncStateMachineBox):System.Runtime.CompilerServices.AsyncStateMachineDispatcher (FullOpts)
          -8 (-2.48 % of base) : System.Private.CoreLib.dasm - System.RuntimeType:GetBaseType():System.RuntimeType:this (FullOpts)
          -7 (-5.43 % of base) : Microsoft.CodeAnalysis.CSharp.Features.dasm - Microsoft.CodeAnalysis.CSharp.Completion.Providers.DeclarationName.NameDeclarationInfo:GetPossibleLocalDeclarations(Microsoft.CodeAnalysis.Editing.DeclarationModifiers):System.Collections.Immutable.ImmutableArray`1[Microsoft.CodeAnalysis.Diagnostics.Analyzers.NamingStyles.SymbolSpecification+SymbolKindOrTypeKind] (FullOpts)
          -6 (-0.10 % of base) : NetTopologySuite.dasm - RTools_NTS.Util.StreamTokenizer:NextToken(byref):bool:this (FullOpts)
          -6 (-35.29 % of base) : System.Reflection.Emit.dasm - System.Reflection.Emit.ModuleBuilderImpl:IsInstance(int):bool (FullOpts)
          -5 (-0.47 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.SM3Digest:ProcessBlock():this (FullOpts)
          -5 (-0.48 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.SM3Digest:ProcessBlock():this (FullOpts)
          -3 (-15.79 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.LongDigest:Maj(ulong,ulong,ulong):ulong (FullOpts)
          -3 (-15.79 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.LongDigest:Maj(ulong,ulong,ulong):ulong (FullOpts)
          -2 (-15.38 % of base) : MailKit.dasm - MailKit.Security.Ntlm.MD4:G(uint,uint,uint):uint (FullOpts)
          -2 (-5.56 % of base) : MailKit.dasm - MailKit.Security.Ntlm.MD4:GG(byref,uint,uint,uint,uint,byte) (FullOpts)
          -2 (-15.38 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.MD4Digest:G(int,int,int):int:this (FullOpts)
          -2 (-15.38 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.MD4Digest:G(int,int,int):int:this (FullOpts)
          -2 (-15.38 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.Sha1Digest:G(uint,uint,uint):uint (FullOpts)
          -2 (-15.38 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.Sha1Digest:G(uint,uint,uint):uint (FullOpts)
          -2 (-15.38 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.Sha224Digest:Maj(uint,uint,uint):uint (FullOpts)
          -2 (-15.38 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.Sha224Digest:Maj(uint,uint,uint):uint (FullOpts)
          -2 (-15.38 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.SM3Digest:FF1(uint,uint,uint):uint:this (FullOpts)
          -2 (-15.38 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.SM3Digest:FF1(uint,uint,uint):uint:this (FullOpts)
          -2 (-15.38 % of base) : System.Net.Security.dasm - System.Net.Security.MD4:G(uint,uint,uint):uint (FullOpts)
          -2 (-5.56 % of base) : System.Net.Security.dasm - System.Net.Security.MD4:GG(byref,uint,uint,uint,uint,byte) (FullOpts)
          -2 (-2.20 % of base) : System.Private.CoreLib.dasm - System.Single:IsEvenInteger(float):bool (FullOpts)

Top method improvements (percentages):
          -6 (-35.29 % of base) : System.Reflection.Emit.dasm - System.Reflection.Emit.ModuleBuilderImpl:IsInstance(int):bool (FullOpts)
          -3 (-15.79 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.LongDigest:Maj(ulong,ulong,ulong):ulong (FullOpts)
          -3 (-15.79 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.LongDigest:Maj(ulong,ulong,ulong):ulong (FullOpts)
          -2 (-15.38 % of base) : MailKit.dasm - MailKit.Security.Ntlm.MD4:G(uint,uint,uint):uint (FullOpts)
          -2 (-15.38 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.MD4Digest:G(int,int,int):int:this (FullOpts)
          -2 (-15.38 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.MD4Digest:G(int,int,int):int:this (FullOpts)
          -2 (-15.38 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.Sha1Digest:G(uint,uint,uint):uint (FullOpts)
          -2 (-15.38 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.Sha1Digest:G(uint,uint,uint):uint (FullOpts)
          -2 (-15.38 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.Sha224Digest:Maj(uint,uint,uint):uint (FullOpts)
          -2 (-15.38 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.Sha224Digest:Maj(uint,uint,uint):uint (FullOpts)
          -2 (-15.38 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.SM3Digest:FF1(uint,uint,uint):uint:this (FullOpts)
          -2 (-15.38 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.SM3Digest:FF1(uint,uint,uint):uint:this (FullOpts)
          -2 (-15.38 % of base) : System.Net.Security.dasm - System.Net.Security.MD4:G(uint,uint,uint):uint (FullOpts)
          -8 (-10.96 % of base) : StackExchange.Redis.dasm - StackExchange.Redis.RedisDatabase:ValidateStringIncrementExpiry(StackExchange.Redis.Expiration) (FullOpts)
        -185 (-10.09 % of base) : System.Net.Security.dasm - System.Net.Security.MD4:MD4Transform(System.Span`1[uint],System.ReadOnlySpan`1[byte]) (FullOpts)
          -9 (-9.09 % of base) : StackExchange.Redis.dasm - StackExchange.Redis.RedisDatabase+IncrexMessageBase:get_ArgCount():int:this (FullOpts)
         -44 (-7.71 % of base) : Microsoft.CodeAnalysis.CSharp.Features.dasm - Microsoft.CodeAnalysis.CSharp.Completion.Providers.DeclarationName.NameDeclarationInfo:GetPossibleMemberDeclarations(Microsoft.CodeAnalysis.Editing.DeclarationModifiers):System.Collections.Immutable.ImmutableArray`1[Microsoft.CodeAnalysis.Diagnostics.Analyzers.NamingStyles.SymbolSpecification+SymbolKindOrTypeKind] (FullOpts)
        -136 (-7.68 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.LongDigest:ProcessBlock():this (FullOpts)
        -136 (-7.68 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.LongDigest:ProcessBlock():this (FullOpts)
         -87 (-5.75 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.Sha224Digest:ProcessBlock():this (FullOpts)
         -87 (-5.75 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.Sha224Digest:ProcessBlock():this (FullOpts)
          -2 (-5.56 % of base) : MailKit.dasm - MailKit.Security.Ntlm.MD4:GG(byref,uint,uint,uint,uint,byte) (FullOpts)
          -2 (-5.56 % of base) : System.Net.Security.dasm - System.Net.Security.MD4:GG(byref,uint,uint,uint,uint,byte) (FullOpts)
          -7 (-5.43 % of base) : Microsoft.CodeAnalysis.CSharp.Features.dasm - Microsoft.CodeAnalysis.CSharp.Completion.Providers.DeclarationName.NameDeclarationInfo:GetPossibleLocalDeclarations(Microsoft.CodeAnalysis.Editing.DeclarationModifiers):System.Collections.Immutable.ImmutableArray`1[Microsoft.CodeAnalysis.Diagnostics.Analyzers.NamingStyles.SymbolSpecification+SymbolKindOrTypeKind] (FullOpts)
         -10 (-5.10 % of base) : System.Runtime.InteropServices.dasm - System.Runtime.InteropServices.Marshalling.StrategyBasedComWrappers:CreateObject(nint,int):System.Object:this (FullOpts)
         -10 (-4.90 % of base) : NuGet.Protocol.dasm - NuGet.Protocol.Plugins.PluginDiscoverer:IsValidPluginFile(System.IO.FileInfo):bool (FullOpts)
         -18 (-4.26 % of base) : Microsoft.CodeAnalysis.Features.dasm - Microsoft.CodeAnalysis.EditAndContinue.AbstractEditAndContinueAnalyzer:AllowsDeletion(Microsoft.CodeAnalysis.ISymbol):bool (FullOpts)
         -16 (-3.46 % of base) : Microsoft.CodeAnalysis.AnalyzerUtilities.dasm - Microsoft.CodeAnalysis.FlowAnalysis.DataFlow.PointsToAnalysis.PointsToAnalysis+PointsToDataFlowOperationVisitor:<SetValueForNullCompareFromPredicate>g__SetAbstractValueFromPredicate|46_0(Microsoft.CodeAnalysis.FlowAnalysis.DataFlow.AnalysisEntity,int,Microsoft.CodeAnalysis.ITypeSymbol,Microsoft.CodeAnalysis.FlowAnalysis.DataFlow.PointsToAnalysis.DefaultPointsToValueGenerator,Microsoft.CodeAnalysis.Compilation,Microsoft.CodeAnalysis.FlowAnalysis.DataFlow.PointsToAnalysis.PointsToAnalysisData,Microsoft.CodeAnalysis.FlowAnalysis.DataFlow.PointsToAnalysis.PointsToAnalysisData) (FullOpts)
         -80 (-3.31 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.MD4Digest:ProcessBlock():this (FullOpts)
         -80 (-3.31 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.MD4Digest:ProcessBlock():this (FullOpts)
          -8 (-3.21 % of base) : System.Private.CoreLib.dasm - System.Runtime.CompilerServices.AsyncStateMachineDispatcherInfo:CreateDispatcher(System.Runtime.CompilerServices.IAsyncStateMachineBox):System.Runtime.CompilerServices.AsyncStateMachineDispatcher (FullOpts)
         -84 (-3.19 % of base) : MailKit.dasm - MailKit.Security.Ntlm.MD4:MD4Transform(byte[],int):this (FullOpts)
         -13 (-2.84 % of base) : System.Private.CoreLib.dasm - System.Sha1ForNonSecretPurposes:Drain(System.Span`1[uint]) (FullOpts)
          -8 (-2.48 % of base) : System.Private.CoreLib.dasm - System.RuntimeType:GetBaseType():System.RuntimeType:this (FullOpts)
          -2 (-2.20 % of base) : System.Private.CoreLib.dasm - System.Single:IsEvenInteger(float):bool (FullOpts)
         -52 (-2.00 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.Sha1Digest:ProcessBlock():this (FullOpts)
         -52 (-2.00 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.Sha1Digest:ProcessBlock():this (FullOpts)
          -9 (-1.87 % of base) : System.Private.Xml.dasm - System.Xml.Schema.XmlSchemaValidator:.ctor(System.Xml.XmlNameTable,System.Xml.Schema.XmlSchemaSet,System.Xml.IXmlNamespaceResolver,int):this (FullOpts)
         -19 (-1.16 % of base) : System.Private.Uri.dasm - System.Uri:ParseRemaining():this (FullOpts)
         -10 (-0.96 % of base) : System.Security.Claims.dasm - System.Security.Claims.Claim:WriteTo(System.IO.BinaryWriter,byte[]):this (FullOpts)
         -10 (-0.62 % of base) : System.IO.Pipelines.dasm - System.IO.Pipelines.PipeReader+<ReadAtLeastAsyncCore>d__4:MoveNext():this (FullOpts)
          -5 (-0.48 % of base) : BouncyCastle.Crypto.dasm - Org.BouncyCastle.Crypto.Digests.SM3Digest:ProcessBlock():this (FullOpts)
          -5 (-0.47 % of base) : BouncyCastle.Cryptography.dasm - Org.BouncyCastle.Crypto.Digests.SM3Digest:ProcessBlock():this (FullOpts)
          -6 (-0.10 % of base) : NetTopologySuite.dasm - RTools_NTS.Util.StreamTokenizer:NextToken(byref):bool:this (FullOpts)
         -18 (-0.08 % of base) : Iced.dasm - Iced.Intel.InstructionInfoFactory:AddImpliedAccesses(int,byref,uint):this (FullOpts)

45 total methods with Code Size differences (45 improved, 0 regressed), 2057422 unchanged.

--------------------------------------------------------------------------------

Artifacts:

Activity

  1. MihuBot commented on Jul 1, 2026

    @MihuBot
    MihuBot
    on Jul 1, 2026
    OwnerAuthor

    Top method improvements

    -185 (-10.09 % of base) - System.Net.Security.MD4:MD4Transform(System.Span`1[uint],System.ReadOnlySpan`1[byte]) 
     ; Assembly listing for method System.Net.Security.MD4:MD4Transform(System.Span`1[uint],System.ReadOnlySpan`1[byte]) (FullOpts)
 ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix
 ; FullOpts code
 ; optimized code
 ; rbp based frame
 ; partially interruptible
 ; No PGO data
 ; 0 inlinees with PGO data; 96 single block inlinees; 1 inlinees without PGO data
 ; Final local variable assignments
 ;
 ;* V00 arg0         [V00    ] (  0,  0   )  struct (16) zero-ref    do-not-enreg[SFA] multireg-arg ld-addr-op single-def ptr <System.Span`1[uint]>
 ;  V01 arg1         [V01,T06] (  4,  4   )  struct (16) [rbp-0x40]  do-not-enreg[SFA] multireg-arg single-def <System.ReadOnlySpan`1[byte]>
-;  V02 loc0         [V02,T00] ( 95, 94   )     int  ->  registers   ld-addr-op
-;  V03 loc1         [V03,T01] ( 95, 94   )     int  ->  registers   ld-addr-op
-;  V04 loc2         [V04,T02] ( 95, 94   )     int  ->  registers   ld-addr-op
-;  V05 loc3         [V05,T03] ( 95, 94   )     int  ->  registers   ld-addr-op
+;  V02 loc0         [V02,T00] ( 99, 98   )     int  ->  r15         ld-addr-op
+;  V03 loc1         [V03,T01] ( 99, 98   )     int  ->  r14         ld-addr-op
+;  V04 loc2         [V04,T02] ( 98, 97   )     int  ->  r13         ld-addr-op
+;  V05 loc3         [V05,T03] ( 98, 97   )     int  ->  r12         ld-addr-op
 ;* V06 loc4         [V06    ] (  0,  0   )  struct (16) zero-ref    ld-addr-op <System.Span`1[uint]>
 ;# V07 OutArgs      [V07    ] (  1,  1   )  struct ( 0) [rsp+0x00]  do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
 ;* V08 tmp1         [V08    ] (  0,  0   )  struct (16) zero-ref    multireg-arg ld-addr-op "NewObj constructor temp" <System.Span`1[uint]>
 ;* V09 tmp2         [V09    ] (  0,  0   )   byref  ->  zero-ref    single-def "dup spill"
 ;  V10 tmp3         [V10,T07] (  3,  6   )   byref  ->   r9         single-def "dup spill"
 ;  V11 tmp4         [V11,T08] (  3,  6   )   byref  ->   r9         single-def "dup spill"
 ;  V12 tmp5         [V12,T09] (  3,  6   )   byref  ->  rbx         single-def "dup spill"
 ;* V13 tmp6         [V13    ] (  0,  0   )    long  ->  zero-ref    "Inlining Arg"
 ;* V14 tmp7         [V14    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V15 tmp8         [V15    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V16 tmp9         [V16    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V17 tmp10        [V17    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V18 tmp11        [V18    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V19 tmp12        [V19    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V20 tmp13        [V20    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V21 tmp14        [V21    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V22 tmp15        [V22    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V23 tmp16        [V23    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V24 tmp17        [V24    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V25 tmp18        [V25    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V26 tmp19        [V26    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V27 tmp20        [V27    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V28 tmp21        [V28    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V29 tmp22        [V29    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V30 tmp23        [V30    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V31 tmp24        [V31    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V32 tmp25        [V32    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V33 tmp26        [V33    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V34 tmp27        [V34    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V35 tmp28        [V35    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V36 tmp29        [V36    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V37 tmp30        [V37    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V38 tmp31        [V38    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V39 tmp32        [V39    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V40 tmp33        [V40    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V41 tmp34        [V41    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V42 tmp35        [V42    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V43 tmp36        [V43    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V44 tmp37        [V44    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V45 tmp38        [V45    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V46 tmp39        [V46    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V47 tmp40        [V47    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V48 tmp41        [V48    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V49 tmp42        [V49    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V50 tmp43        [V50    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V51 tmp44        [V51    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V52 tmp45        [V52    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V53 tmp46        [V53    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V54 tmp47        [V54    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V55 tmp48        [V55    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V56 tmp49        [V56    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V57 tmp50        [V57    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V58 tmp51        [V58    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V59 tmp52        [V59    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V60 tmp53        [V60    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V61 tmp54        [V61    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V62 tmp55        [V62    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V63 tmp56        [V63    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V64 tmp57        [V64    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V65 tmp58        [V65    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V66 tmp59        [V66    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V67 tmp60        [V67    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V68 tmp61        [V68    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V69 tmp62        [V69    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V70 tmp63        [V70    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V71 tmp64        [V71    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V72 tmp65        [V72    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V73 tmp66        [V73    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V74 tmp67        [V74    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V75 tmp68        [V75    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V76 tmp69        [V76    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V77 tmp70        [V77    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V78 tmp71        [V78    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V79 tmp72        [V79    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V80 tmp73        [V80    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V81 tmp74        [V81    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V82 tmp75        [V82    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V83 tmp76        [V83    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V84 tmp77        [V84    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V85 tmp78        [V85    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V86 tmp79        [V86    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V87 tmp80        [V87    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V88 tmp81        [V88    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V89 tmp82        [V89    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V90 tmp83        [V90    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V91 tmp84        [V91    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V92 tmp85        [V92    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V93 tmp86        [V93    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V94 tmp87        [V94    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V95 tmp88        [V95    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V96 tmp89        [V96    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V97 tmp90        [V97    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V98 tmp91        [V98    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V99 tmp92        [V99    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V100 tmp93       [V100    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V101 tmp94       [V101    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V102 tmp95       [V102    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V103 tmp96       [V103    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V104 tmp97       [V104    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V105 tmp98       [V105    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V106 tmp99       [V106    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V107 tmp100      [V107    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V108 tmp101      [V108    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V109 tmp102      [V109    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V110 tmp103      [V110    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V111 tmp104      [V111    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V112 tmp105      [V112    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V113 tmp106      [V113    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V114 tmp107      [V114    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V115 tmp108      [V115    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V116 tmp109      [V116    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V117 tmp110      [V117    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V118 tmp111      [V118    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V119 tmp112      [V119    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V120 tmp113      [V120    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V121 tmp114      [V121    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V122 tmp115      [V122    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V123 tmp116      [V123    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V124 tmp117      [V124    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V125 tmp118      [V125    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V126 tmp119      [V126    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V127 tmp120      [V127    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V128 tmp121      [V128    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V129 tmp122      [V129    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V130 tmp123      [V130    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V131 tmp124      [V131    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V132 tmp125      [V132    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V133 tmp126      [V133    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V134 tmp127      [V134    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V135 tmp128      [V135    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V136 tmp129      [V136    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V137 tmp130      [V137    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V138 tmp131      [V138    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V139 tmp132      [V139    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V140 tmp133      [V140    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V141 tmp134      [V141    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V142 tmp135      [V142    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V143 tmp136      [V143    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V144 tmp137      [V144    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V145 tmp138      [V145    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V146 tmp139      [V146    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V147 tmp140      [V147    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V148 tmp141      [V148    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V149 tmp142      [V149    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V150 tmp143      [V150    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V151 tmp144      [V151    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V152 tmp145      [V152    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V153 tmp146      [V153    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V154 tmp147      [V154    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V155 tmp148      [V155    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V156 tmp149      [V156    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V157 tmp150      [V157    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V158 tmp151      [V158    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V159 tmp152      [V159    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V160 tmp153      [V160    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V161 tmp154      [V161    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V162 tmp155      [V162    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V163 tmp156      [V163    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V164 tmp157      [V164    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V165 tmp158      [V165    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V166 tmp159      [V166    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V167 tmp160      [V167    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V168 tmp161      [V168    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V169 tmp162      [V169    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V170 tmp163      [V170    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V171 tmp164      [V171    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V172 tmp165      [V172    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V173 tmp166      [V173    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V174 tmp167      [V174    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V175 tmp168      [V175    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V176 tmp169      [V176    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V177 tmp170      [V177    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V178 tmp171      [V178    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V179 tmp172      [V179    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V180 tmp173      [V180    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V181 tmp174      [V181    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V182 tmp175      [V182    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V183 tmp176      [V183    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V184 tmp177      [V184    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V185 tmp178      [V185    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V186 tmp179      [V186    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V187 tmp180      [V187    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V188 tmp181      [V188    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V189 tmp182      [V189    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V190 tmp183      [V190    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V191 tmp184      [V191    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V192 tmp185      [V192    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V193 tmp186      [V193    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V194 tmp187      [V194    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V195 tmp188      [V195    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V196 tmp189      [V196    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V197 tmp190      [V197    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V198 tmp191      [V198    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V199 tmp192      [V199    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V200 tmp193      [V200    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V201 tmp194      [V201    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V202 tmp195      [V202    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V203 tmp196      [V203    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V204 tmp197      [V204    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V205 tmp198      [V205    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V206 tmp199      [V206    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V207 tmp200      [V207    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V208 tmp201      [V208    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V209 tmp202      [V209    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V210 tmp203      [V210    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V211 tmp204      [V211    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V212 tmp205      [V212    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V213 tmp206      [V213    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V214 tmp207      [V214    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V215 tmp208      [V215    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V216 tmp209      [V216    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V217 tmp210      [V217    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V218 tmp211      [V218    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V219 tmp212      [V219    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V220 tmp213      [V220    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V221 tmp214      [V221    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V222 tmp215      [V222    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V223 tmp216      [V223    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V224 tmp217      [V224    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V225 tmp218      [V225    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V226 tmp219      [V226    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V227 tmp220      [V227    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V228 tmp221      [V228    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V229 tmp222      [V229    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V230 tmp223      [V230    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V231 tmp224      [V231    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V232 tmp225      [V232    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V233 tmp226      [V233    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V234 tmp227      [V234    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V235 tmp228      [V235    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V236 tmp229      [V236    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V237 tmp230      [V237    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V238 tmp231      [V238    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V239 tmp232      [V239    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V240 tmp233      [V240    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V241 tmp234      [V241    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V242 tmp235      [V242    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V243 tmp236      [V243    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V244 tmp237      [V244    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V245 tmp238      [V245    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V246 tmp239      [V246    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V247 tmp240      [V247    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V248 tmp241      [V248    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V249 tmp242      [V249    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V250 tmp243      [V250    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V251 tmp244      [V251    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V252 tmp245      [V252    ] (  0,  0   )     int  ->  zero-ref    "impAppendStmt"
 ;* V253 tmp246      [V253    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V254 tmp247      [V254    ] (  0,  0   )   byref  ->  zero-ref    single-def "field V06._reference (fldOffset=0x0)" P-INDEP
 ;* V255 tmp248      [V255    ] (  0,  0   )     int  ->  zero-ref    "field V06._length (fldOffset=0x8)" P-INDEP
-;  V256 tmp249      [V256,T04] ( 18, 18   )   byref  ->  [rbp-0xB0]  spill-single-def ptr "field V08._reference (fldOffset=0x0)" P-INDEP
+;  V256 tmp249      [V256,T04] ( 18, 18   )   byref  ->  [rbp-0x70]  spill-single-def ptr "field V08._reference (fldOffset=0x0)" P-INDEP
 ;* V257 tmp250      [V257    ] (  0,  0   )     int  ->  zero-ref    "field V08._length (fldOffset=0x8)" P-INDEP
 ;  V258 tmp251      [V258,T05] ( 14, 10   )   byref  ->  rbx         single-def "V00.[000..008)"
-;  V259 tmp252      [V259,T44] (  6,  2   )     int  ->  rsi         "V00.[008..012)"
-;  V260 cse0        [V260,T10] (  4,  4   )     int  ->   r8         "CSE #04: moderate"
-;  V261 cse1        [V261,T11] (  4,  4   )     int  ->  rsi         "CSE #06: moderate"
-;  V262 cse2        [V262,T12] (  4,  4   )     int  ->  rdi         "CSE #08: moderate"
-;  V263 cse3        [V263,T13] (  4,  4   )     int  ->  rcx         "CSE #10: moderate"
-;  V264 cse4        [V264,T14] (  4,  4   )     int  ->  [rbp-0x44]  spill-single-def "CSE #12: moderate"
-;  V265 cse5        [V265,T15] (  4,  4   )     int  ->  [rbp-0x48]  spill-single-def "CSE #14: moderate"
-;  V266 cse6        [V266,T16] (  4,  4   )     int  ->  [rbp-0x4C]  spill-single-def "CSE #16: moderate"
-;  V267 cse7        [V267,T17] (  4,  4   )     int  ->  [rbp-0x50]  spill-single-def "CSE #18: moderate"
-;  V268 cse8        [V268,T18] (  4,  4   )     int  ->  [rbp-0x54]  spill-single-def "CSE #20: moderate"
-;  V269 cse9        [V269,T19] (  4,  4   )     int  ->  [rbp-0x58]  spill-single-def "CSE #22: moderate"
-;  V270 cse10       [V270,T20] (  4,  4   )     int  ->  r11         "CSE #24: moderate"
-;  V271 cse11       [V271,T21] (  4,  4   )     int  ->  [rbp-0x5C]  spill-single-def "CSE #26: moderate"
-;  V272 cse12       [V272,T22] (  4,  4   )     int  ->  [rbp-0x60]  spill-single-def "CSE #28: moderate"
-;  V273 cse13       [V273,T23] (  4,  4   )     int  ->  [rbp-0x64]  spill-single-def "CSE #30: moderate"
-;  V274 cse14       [V274,T24] (  4,  4   )     int  ->   r9         "CSE #32: moderate"
-;  V275 cse15       [V275,T25] (  4,  4   )     int  ->  rax         "CSE #02: moderate"
+;  V259 tmp252      [V259,T29] (  6,  2   )     int  ->  rsi         "V00.[008..012)"
+;  V260 cse0        [V260,T10] (  4,  4   )     int  ->   r8         "CSE #03: moderate"
+;  V261 cse1        [V261,T11] (  4,  4   )     int  ->  rsi         "CSE #04: moderate"
+;  V262 cse2        [V262,T12] (  4,  4   )     int  ->  rdi         "CSE #05: moderate"
+;  V263 cse3        [V263,T13] (  4,  4   )     int  ->  rcx         "CSE #06: moderate"
+;  V264 cse4        [V264,T14] (  4,  4   )     int  ->  r10         "CSE #07: moderate"
+;  V265 cse5        [V265,T15] (  4,  4   )     int  ->  [rbp-0x44]  spill-single-def "CSE #08: moderate"
+;  V266 cse6        [V266,T16] (  4,  4   )     int  ->  [rbp-0x48]  spill-single-def "CSE #09: moderate"
+;  V267 cse7        [V267,T17] (  4,  4   )     int  ->  [rbp-0x4C]  spill-single-def "CSE #10: moderate"
+;  V268 cse8        [V268,T18] (  4,  4   )     int  ->  [rbp-0x50]  spill-single-def "CSE #11: moderate"
+;  V269 cse9        [V269,T19] (  4,  4   )     int  ->  [rbp-0x54]  spill-single-def "CSE #12: moderate"
+;  V270 cse10       [V270,T20] (  4,  4   )     int  ->  r11         "CSE #13: moderate"
+;  V271 cse11       [V271,T21] (  4,  4   )     int  ->  [rbp-0x58]  spill-single-def "CSE #14: moderate"
+;  V272 cse12       [V272,T22] (  4,  4   )     int  ->  [rbp-0x5C]  spill-single-def "CSE #15: moderate"
+;  V273 cse13       [V273,T23] (  4,  4   )     int  ->  [rbp-0x60]  spill-single-def "CSE #16: moderate"
+;  V274 cse14       [V274,T24] (  4,  4   )     int  ->   r9         "CSE #17: moderate"
+;  V275 cse15       [V275,T25] (  4,  4   )     int  ->  [rbp-0x64]  spill-single-def "CSE #02: moderate"
 ;  V276 cse16       [V276,T27] (  3,  3   )     int  ->  [rbp-0x68]  spill-single-def "CSE #01: moderate"
-;  V277 cse17       [V277,T28] (  3,  3   )     int  ->  [rbp-0x6C]  spill-single-def "CSE #03: moderate"
-;  V278 cse18       [V278,T29] (  3,  3   )     int  ->  [rbp-0x70]  spill-single-def "CSE #05: moderate"
-;  V279 cse19       [V279,T30] (  3,  3   )     int  ->  [rbp-0x74]  spill-single-def "CSE #07: moderate"
-;  V280 cse20       [V280,T31] (  3,  3   )     int  ->  [rbp-0x78]  spill-single-def "CSE #09: moderate"
-;  V281 cse21       [V281,T32] (  3,  3   )     int  ->  [rbp-0x7C]  spill-single-def "CSE #11: moderate"
-;  V282 cse22       [V282,T33] (  3,  3   )     int  ->  [rbp-0x80]  spill-single-def "CSE #13: moderate"
-;  V283 cse23       [V283,T34] (  3,  3   )     int  ->  [rbp-0x84]  spill-single-def "CSE #15: moderate"
-;  V284 cse24       [V284,T35] (  3,  3   )     int  ->  [rbp-0x88]  spill-single-def "CSE #17: moderate"
-;  V285 cse25       [V285,T36] (  3,  3   )     int  ->  [rbp-0x8C]  spill-single-def "CSE #19: moderate"
-;  V286 cse26       [V286,T37] (  3,  3   )     int  ->  [rbp-0x90]  spill-single-def "CSE #21: moderate"
-;  V287 cse27       [V287,T38] (  3,  3   )     int  ->  [rbp-0x94]  spill-single-def "CSE #23: moderate"
-;  V288 cse28       [V288,T39] (  3,  3   )     int  ->  [rbp-0x98]  spill-single-def "CSE #25: moderate"
-;  V289 cse29       [V289,T40] (  3,  3   )     int  ->  [rbp-0x9C]  spill-single-def "CSE #27: moderate"
-;  V290 cse30       [V290,T41] (  3,  3   )     int  ->  [rbp-0xA0]  spill-single-def "CSE #29: moderate"
-;  V291 cse31       [V291,T42] (  3,  3   )     int  ->  [rbp-0xA4]  spill-single-def "CSE #31: moderate"
-;  V292 rat0        [V292    ] (  1,  1   )    long  ->  [rbp-0x30]  do-not-enreg[X] addr-exposed "GSSecurityCookie"
-;  V293 rat1        [V293,T26] (  3,  3   )   byref  ->  rdi         "V00.rdi"
-;  V294 rat2        [V294,T43] (  3,  3   )    long  ->  rsi         "V00.rsi"
+;  V277 rat0        [V277    ] (  1,  1   )    long  ->  [rbp-0x30]  do-not-enreg[X] addr-exposed "GSSecurityCookie"
+;  V278 rat1        [V278,T26] (  3,  3   )   byref  ->  rdi         "V00.rdi"
+;  V279 rat2        [V279,T28] (  3,  3   )    long  ->  rsi         "V00.rsi"
 ;
-; Lcl frame size = 136
+; Lcl frame size = 72
 
 G_M35977_IG01:
        push     rbp
        push     r15
        push     r14
        push     r13
        push     r12
        push     rbx
-       sub      rsp, 136
-       lea      rbp, [rsp+0xB0]
+       sub      rsp, 72
+       lea      rbp, [rsp+0x70]
        mov      rax, 0xD1FFAB1E
        mov      qword ptr [rbp-0x30], rax
        mov      bword ptr [rbp-0x40], rdx
        mov      qword ptr [rbp-0x38], rcx
-						;; size=47 bbWeight=1 PerfScore 10.00
+						;; size=41 bbWeight=1 PerfScore 10.00
 G_M35977_IG02:
        mov      rbx, rdi
        cmp      esi, 3
-       jle      G_M35977_IG12
+       jle      G_M35977_IG11
        mov      r15d, dword ptr [rbx]
        mov      r14d, dword ptr [rbx+0x04]
        mov      r13d, dword ptr [rbx+0x08]
        mov      r12d, dword ptr [rbx+0x0C]
 						;; size=27 bbWeight=1 PerfScore 9.50
 G_M35977_IG03:
        test     dword ptr [rsp], esp
        sub      rsp, 64
        lea      rax, [rsp]
-       mov      bword ptr [rbp-0xB0], rax
+       mov      bword ptr [rbp-0x70], rax
        mov      rdx, bword ptr [rbp-0x40]
        mov      rcx, qword ptr [rbp-0x38]
        mov      rdi, rax
        mov      esi, 16
        mov      r8, 0xD1FFAB1E      ; code for System.Net.Security.MD4:Decode(System.Span`1[uint],System.ReadOnlySpan`1[byte])
        call     [r8]System.Net.Security.MD4:Decode(System.Span`1[uint],System.ReadOnlySpan`1[byte])
        mov      r9d, r14d
        and      r9d, r13d
        andn     eax, r14d, r12d
        or       r9d, eax
        add      r15d, r9d
-       mov      r9, bword ptr [rbp-0xB0]
+       mov      r9, bword ptr [rbp-0x70]
        mov      eax, dword ptr [r9]
+       mov      dword ptr [rbp-0x64], eax
        add      r15d, eax
        rol      r15d, 3
        mov      ecx, r15d
        and      ecx, r14d
        andn     edx, r15d, r13d
        or       ecx, edx
        add      r12d, ecx
        mov      ecx, dword ptr [r9+0x04]
        add      r12d, ecx
        rol      r12d, 7
        mov      edx, r12d
        and      edx, r15d
        andn     edi, r12d, r14d
        or       edx, edi
        add      r13d, edx
        mov      edx, dword ptr [r9+0x08]
-       mov      dword ptr [rbp-0x50], edx
+       mov      dword ptr [rbp-0x4C], edx
        add      r13d, edx
        rol      r13d, 11
        mov      edi, r13d
        and      edi, r12d
        andn     esi, r13d, r15d
        or       edi, esi
        add      r14d, edi
        mov      edi, dword ptr [r9+0x0C]
-       mov      dword ptr [rbp-0x5C], edi
+       mov      dword ptr [rbp-0x58], edi
        add      r14d, edi
        rol      r14d, 19
        mov      esi, r14d
        and      esi, r13d
        andn     r8d, r14d, r12d
        or       esi, r8d
        add      esi, r15d
        mov      r8d, dword ptr [r9+0x10]
        lea      r15d, [rsi+r8]
        rol      r15d, 3
        mov      esi, r15d
        and      esi, r14d
        andn     r10d, r15d, r13d
        or       esi, r10d
        add      esi, r12d
        mov      r10d, dword ptr [r9+0x14]
-       mov      dword ptr [rbp-0x44], r10d
        lea      r12d, [rsi+r10]
        rol      r12d, 7
        mov      esi, r12d
        and      esi, r15d
        andn     r11d, r12d, r14d
        or       esi, r11d
        add      esi, r13d
        mov      r11d, dword ptr [r9+0x18]
-						;; size=251 bbWeight=1 PerfScore 43.00
+						;; size=244 bbWeight=1 PerfScore 43.00
 G_M35977_IG04:
-       mov      dword ptr [rbp-0x54], r11d
+       mov      dword ptr [rbp-0x50], r11d
        lea      r13d, [rsi+r11]
        rol      r13d, 11
        mov      esi, r13d
        and      esi, r12d
        andn     edi, r13d, r15d
        or       edi, esi
        add      edi, r14d
        mov      esi, dword ptr [r9+0x1C]
-       mov      dword ptr [rbp-0x60], esi
+       mov      dword ptr [rbp-0x5C], esi
        lea      r14d, [rdi+rsi]
        rol      r14d, 19
        mov      edi, r14d
        and      edi, r13d
        andn     esi, r14d, r12d
        or       edi, esi
        add      edi, r15d
        mov      esi, dword ptr [r9+0x20]
        lea      r15d, [rdi+rsi]
        rol      r15d, 3
        mov      edi, r15d
        and      edi, r14d
        andn     r11d, r15d, r13d
        or       edi, r11d
        add      edi, r12d
        mov      r11d, dword ptr [r9+0x24]
-       mov      dword ptr [rbp-0x48], r11d
+       mov      dword ptr [rbp-0x44], r11d
        lea      r12d, [rdi+r11]
        rol      r12d, 7
        mov      edi, r12d
        and      edi, r15d
        andn     edx, r12d, r14d
        or       edx, edi
        add      edx, r13d
        mov      edi, dword ptr [r9+0x28]
-       mov      dword ptr [rbp-0x58], edi
+       mov      dword ptr [rbp-0x54], edi
        lea      r13d, [rdx+rdi]
        rol      r13d, 11
        mov      edx, r13d
        and      edx, r12d
        andn     edi, r13d, r15d
        or       edx, edi
        add      edx, r14d
        mov      edi, dword ptr [r9+0x2C]
-       mov      dword ptr [rbp-0x64], edi
+       mov      dword ptr [rbp-0x60], edi
        lea      r14d, [rdx+rdi]
        rol      r14d, 19
        mov      edx, r14d
        and      edx, r13d
        andn     edi, r14d, r12d
        or       edx, edi
        add      edx, r15d
        mov      edi, dword ptr [r9+0x30]
        lea      r15d, [rdx+rdi]
        rol      r15d, 3
        mov      edx, r15d
        and      edx, r14d
        andn     r11d, r15d, r13d
        or       edx, r11d
        add      edx, r12d
        mov      r11d, dword ptr [r9+0x34]
-       mov      dword ptr [rbp-0x4C], r11d
+       mov      dword ptr [rbp-0x48], r11d
        lea      r12d, [rdx+r11]
        rol      r12d, 7
        mov      edx, r12d
        and      edx, r15d
        andn     r11d, r12d, r14d
        or       edx, r11d
        add      edx, r13d
        mov      r11d, dword ptr [r9+0x38]
        lea      r13d, [rdx+r11]
 						;; size=252 bbWeight=1 PerfScore 42.50
 G_M35977_IG05:
        rol      r13d, 11
        mov      edx, r13d
        and      edx, r12d
        mov      dword ptr [rbp-0x68], edx
        andn     edx, r13d, r15d
        or       edx, dword ptr [rbp-0x68]
        add      edx, r14d
        mov      r9d, dword ptr [r9+0x3C]
        lea      r14d, [rdx+r9]
        rol      r14d, 19
-       mov      edx, r14d
-       and      edx, r13d
-       mov      dword ptr [rbp-0x6C], edx
-       mov      edx, r14d
-       and      edx, r12d
-       or       edx, dword ptr [rbp-0x6C]
+       mov      edx, r13d
+       or       edx, r12d
+       and      edx, r14d
        or       edx, dword ptr [rbp-0x68]
        add      edx, r15d
        lea      r15d, [rdx+rax+D1FFAB1EH]
        rol      r15d, 3
-       mov      edx, r15d
-       and      edx, r14d
-       mov      dword ptr [rbp-0x70], edx
-       mov      edx, r15d
+       mov      edx, r14d
        and      edx, r13d
-       or       edx, dword ptr [rbp-0x70]
-       or       edx, dword ptr [rbp-0x6C]
-       add      edx, r12d
-       lea      r12d, [rdx+r8+D1FFAB1EH]
+       mov      eax, r14d
+       or       eax, r13d
+       and      eax, r15d
+       or       eax, edx
+       add      eax, r12d
+       lea      r12d, [rax+r8+D1FFAB1EH]
        rol      r12d, 5
-       mov      edx, r12d
-       and      edx, r15d
-       mov      dword ptr [rbp-0x74], edx
-       mov      edx, r12d
-       and      edx, r14d
-       or       edx, dword ptr [rbp-0x74]
-       or       edx, dword ptr [rbp-0x70]
-       add      edx, r13d
-       lea      r13d, [rdx+rsi+D1FFAB1EH]
+       mov      eax, r15d
+       and      eax, r14d
+       mov      edx, r15d
+       or       edx, r14d
+       and      edx, r12d
+       or       eax, edx
+       add      eax, r13d
+       lea      r13d, [rax+rsi+D1FFAB1EH]
        rol      r13d, 9
-       mov      edx, r13d
-       and      edx, r12d
-       mov      dword ptr [rbp-0x78], edx
-       mov      edx, r13d
-       and      edx, r15d
-       or       edx, dword ptr [rbp-0x78]
-       or       edx, dword ptr [rbp-0x74]
-       add      edx, r14d
-       lea      r14d, [rdx+rdi+D1FFAB1EH]
-       rol      r14d, 13
-       mov      edx, r14d
+       mov      eax, r12d
+       and      eax, r15d
+       mov      edx, r12d
+       or       edx, r15d
        and      edx, r13d
-       mov      dword ptr [rbp-0x7C], edx
-       mov      edx, r14d
-       and      edx, r12d
-       or       edx, dword ptr [rbp-0x7C]
-       or       edx, dword ptr [rbp-0x78]
-       add      edx, r15d
-       lea      r15d, [rdx+rcx+D1FFAB1EH]
-       rol      r15d, 3
-       mov      edx, r15d
-       and      edx, r14d
-       mov      dword ptr [rbp-0x80], edx
-       mov      edx, r15d
-       and      edx, r13d
-       or       edx, dword ptr [rbp-0x80]
-       or       edx, dword ptr [rbp-0x7C]
-       add      edx, r12d
-       lea      r12d, [rdx+r10+D1FFAB1EH]
-       rol      r12d, 5
-						;; size=252 bbWeight=1 PerfScore 41.25
-G_M35977_IG06:
-       mov      edx, r12d
-       and      edx, r15d
-       mov      dword ptr [rbp-0x84], edx
-       mov      edx, r12d
-       and      edx, r14d
-       or       edx, dword ptr [rbp-0x84]
-       or       edx, dword ptr [rbp-0x80]
-       add      edx, r13d
-       mov      r13d, dword ptr [rbp-0x48]
-       lea      edx, [rdx+r13+D1FFAB1EH]
-       rol      edx, 9
-       mov      r13d, edx
-       and      r13d, r12d
-       mov      dword ptr [rbp-0x88], r13d
-       mov      r13d, edx
-       and      r13d, r15d
-       or       r13d, dword ptr [rbp-0x88]
-       or       r13d, dword ptr [rbp-0x84]
-       add      r13d, r14d
-       mov      r14d, dword ptr [rbp-0x4C]
-       lea      r13d, [r13+r14+D1FFAB1EH]
-       rol      r13d, 13
-       mov      r14d, r13d
-       and      r14d, edx
-       mov      dword ptr [rbp-0x8C], r14d
-       mov      r14d, r13d
-       and      r14d, r12d
-       or       r14d, dword ptr [rbp-0x8C]
-       or       r14d, dword ptr [rbp-0x88]
-       add      r14d, r15d
-       mov      r15d, dword ptr [rbp-0x50]
-       lea      r14d, [r14+r15+D1FFAB1EH]
-       rol      r14d, 3
-       mov      r15d, r14d
-       and      r15d, r13d
-       mov      dword ptr [rbp-0x90], r15d
-       mov      r15d, r14d
-       and      r15d, edx
-       or       r15d, dword ptr [rbp-0x90]
-       or       r15d, dword ptr [rbp-0x8C]
-       add      r15d, r12d
-       mov      r12d, dword ptr [rbp-0x54]
-       lea      r15d, [r15+r12+D1FFAB1EH]
-       rol      r15d, 5
-       mov      r12d, r15d
-       and      r12d, r14d
-       mov      dword ptr [rbp-0x94], r12d
-       mov      r12d, r15d
-       and      r12d, r13d
-       or       r12d, dword ptr [rbp-0x94]
-       or       r12d, dword ptr [rbp-0x90]
-       add      r12d, edx
-       mov      edx, dword ptr [rbp-0x58]
-       lea      r12d, [r12+rdx+D1FFAB1EH]
-       rol      r12d, 9
-       mov      edx, r12d
-       and      edx, r15d
-       mov      dword ptr [rbp-0x98], edx
-       mov      edx, r12d
-       and      edx, r14d
-       or       edx, dword ptr [rbp-0x98]
-       or       edx, dword ptr [rbp-0x94]
-       add      edx, r13d
-       lea      r13d, [rdx+r11+D1FFAB1EH]
-       rol      r13d, 13
-       mov      edx, r13d
-       and      edx, r12d
-       mov      dword ptr [rbp-0x9C], edx
-       mov      edx, r13d
-       and      edx, r15d
-						;; size=315 bbWeight=1 PerfScore 42.50
-G_M35977_IG07:
-       or       edx, dword ptr [rbp-0x9C]
-       or       edx, dword ptr [rbp-0x98]
-       add      edx, r14d
-       mov      r14d, dword ptr [rbp-0x5C]
-       lea      edx, [rdx+r14+D1FFAB1EH]
-       rol      edx, 3
-       mov      r14d, edx
-       and      r14d, r13d
-       mov      dword ptr [rbp-0xA0], r14d
-       mov      r14d, edx
-       and      r14d, r12d
-       or       r14d, dword ptr [rbp-0xA0]
-       or       r14d, dword ptr [rbp-0x9C]
-       add      r14d, r15d
-       mov      r15d, dword ptr [rbp-0x60]
-       lea      r14d, [r14+r15+D1FFAB1EH]
-       rol      r14d, 5
-       mov      r15d, r14d
-       and      r15d, edx
-       mov      dword ptr [rbp-0xA4], r15d
-       mov      r15d, r14d
-       and      r15d, r13d
-       or       r15d, dword ptr [rbp-0xA4]
-       or       r15d, dword ptr [rbp-0xA0]
-       add      r15d, r12d
-       mov      r12d, dword ptr [rbp-0x64]
-       lea      r15d, [r15+r12+D1FFAB1EH]
-       rol      r15d, 9
-       mov      r12d, r15d
-       and      r12d, r14d
-       mov      r10d, r15d
-       and      r10d, edx
-       or       r10d, r12d
-       or       r10d, dword ptr [rbp-0xA4]
-       add      r10d, r13d
-       lea      r13d, [r10+r9+D1FFAB1EH]
-       rol      r13d, 13
-       mov      r10d, r13d
-       xor      r10d, r15d
-       xor      r10d, r14d
-       add      r10d, edx
-       lea      edx, [r10+rax+D1FFAB1EH]
-       rol      edx, 3
-       mov      eax, edx
-       xor      eax, r13d
-       xor      eax, r15d
+       or       eax, edx
        add      eax, r14d
-       lea      r14d, [rax+rsi+D1FFAB1EH]
-       rol      r14d, 9
-       mov      eax, r14d
-       xor      eax, edx
-       xor      eax, r13d
-       add      eax, r15d
-       lea      r15d, [rax+r8+D1FFAB1EH]
-       rol      r15d, 11
-       mov      eax, r15d
-       xor      eax, r14d
-       xor      eax, edx
-       add      eax, r13d
-       lea      r13d, [rax+rdi+D1FFAB1EH]
-       rol      r13d, 15
-       mov      eax, r13d
-       xor      eax, r15d
-       xor      eax, r14d
-       add      eax, edx
-       mov      edx, dword ptr [rbp-0x50]
-       lea      edx, [rax+rdx+D1FFAB1EH]
-       mov      r12d, edx
-       rol      r12d, 3
-       mov      eax, r12d
-       xor      eax, r13d
-       xor      eax, r15d
-       add      eax, r14d
-						;; size=303 bbWeight=1 PerfScore 37.00
-G_M35977_IG08:
-       mov      edx, dword ptr [rbp-0x58]
-       lea      r14d, [rax+rdx+D1FFAB1EH]
-       rol      r14d, 9
-       mov      eax, r14d
-       xor      eax, r12d
-       xor      eax, r13d
-       add      eax, r15d
-       mov      edx, dword ptr [rbp-0x54]
-       lea      r15d, [rax+rdx+D1FFAB1EH]
-       rol      r15d, 11
-       mov      eax, r15d
-       xor      eax, r14d
-       xor      eax, r12d
-       add      eax, r13d
-       lea      r13d, [rax+r11+D1FFAB1EH]
-       rol      r13d, 15
-       mov      eax, r13d
-       xor      eax, r15d
-       xor      eax, r14d
-       add      eax, r12d
-       lea      r12d, [rax+rcx+D1FFAB1EH]
-       rol      r12d, 3
-       mov      eax, r12d
-       xor      eax, r13d
-       xor      eax, r15d
-       add      eax, r14d
-       mov      r11d, dword ptr [rbp-0x48]
-       lea      r14d, [rax+r11+D1FFAB1EH]
-       rol      r14d, 9
-       mov      eax, r14d
-       xor      eax, r12d
-       xor      eax, r13d
-       add      eax, r15d
-       mov      r10d, dword ptr [rbp-0x44]
-       lea      r15d, [rax+r10+D1FFAB1EH]
-       rol      r15d, 11
-       mov      eax, r15d
-       xor      eax, r14d
-       xor      eax, r12d
-       add      eax, r13d
-       mov      r11d, dword ptr [rbp-0x4C]
-       lea      r13d, [rax+r11+D1FFAB1EH]
-       rol      r13d, 15
-       mov      eax, r13d
-       xor      eax, r15d
-       xor      eax, r14d
-       add      eax, r12d
-       mov      edi, dword ptr [rbp-0x5C]
-       lea      r12d, [rax+rdi+D1FFAB1EH]
-       rol      r12d, 3
-       mov      eax, r12d
-       xor      eax, r13d
-       xor      eax, r15d
-       add      eax, r14d
-       mov      edi, dword ptr [rbp-0x64]
        lea      r14d, [rax+rdi+D1FFAB1EH]
-       rol      r14d, 9
-       mov      eax, r14d
-       xor      eax, r12d
-       xor      eax, r13d
+       rol      r14d, 13
+       mov      eax, r13d
+       and      eax, r12d
+       mov      edx, r13d
+       or       edx, r12d
+       and      edx, r14d
+       or       eax, edx
        add      eax, r15d
-       mov      r15d, dword ptr [rbp-0x60]
-       lea      r15d, [rax+r15+D1FFAB1EH]
-       rol      r15d, 11
+       lea      r15d, [rax+rcx+D1FFAB1EH]
+       rol      r15d, 3
+       mov      eax, r14d
+       and      eax, r13d
+       mov      edx, r14d
+       or       edx, r13d
+       and      edx, r15d
+       or       eax, edx
+       add      eax, r12d
+       lea      r12d, [rax+r10+D1FFAB1EH]
+       rol      r12d, 5
+       mov      eax, r15d
+       and      eax, r14d
+       mov      edx, r15d
+       or       edx, r14d
+       and      edx, r12d
+       or       eax, edx
+       add      eax, r13d
+       mov      edx, dword ptr [rbp-0x44]
+       lea      r13d, [rax+rdx+D1FFAB1EH]
+       rol      r13d, 9
+       mov      eax, r12d
+       and      eax, r15d
+       mov      edx, r12d
+       or       edx, r15d
+       and      edx, r13d
+						;; size=273 bbWeight=1 PerfScore 32.00
+G_M35977_IG06:
+       or       eax, edx
+       add      eax, r14d
+       mov      edx, dword ptr [rbp-0x48]
+       lea      r14d, [rax+rdx+D1FFAB1EH]
+       rol      r14d, 13
+       mov      eax, r13d
+       and      eax, r12d
+       mov      edx, r13d
+       or       edx, r12d
+       and      edx, r14d
+       or       eax, edx
+       add      eax, r15d
+       mov      edx, dword ptr [rbp-0x4C]
+       lea      r15d, [rax+rdx+D1FFAB1EH]
+       rol      r15d, 3
+       mov      eax, r14d
+       and      eax, r13d
+       mov      edx, r14d
+       or       edx, r13d
+       and      edx, r15d
+       or       eax, edx
+       add      eax, r12d
+       mov      edx, dword ptr [rbp-0x50]
+       lea      r12d, [rax+rdx+D1FFAB1EH]
+       rol      r12d, 5
+       mov      eax, r15d
+       and      eax, r14d
+       mov      edx, r15d
+       or       edx, r14d
+       and      edx, r12d
+       or       eax, edx
+       add      eax, r13d
+       mov      edx, dword ptr [rbp-0x54]
+       lea      r13d, [rax+rdx+D1FFAB1EH]
+       rol      r13d, 9
+       mov      eax, r12d
+       and      eax, r15d
+       mov      edx, r12d
+       or       edx, r15d
+       and      edx, r13d
+       or       eax, edx
+       add      eax, r14d
+       lea      r14d, [rax+r11+D1FFAB1EH]
+       rol      r14d, 13
+       mov      eax, r13d
+       and      eax, r12d
+       mov      edx, r13d
+       or       edx, r12d
+       and      edx, r14d
+       or       eax, edx
+       add      eax, r15d
+       mov      edx, dword ptr [rbp-0x58]
+       lea      r15d, [rax+rdx+D1FFAB1EH]
+       rol      r15d, 3
+       mov      eax, r14d
+       and      eax, r13d
+       mov      edx, r14d
+       or       edx, r13d
+       and      edx, r15d
+       or       eax, edx
+       add      eax, r12d
+       mov      edx, dword ptr [rbp-0x5C]
+       lea      r12d, [rax+rdx+D1FFAB1EH]
+       rol      r12d, 5
+       mov      eax, r15d
+       and      eax, r14d
+       mov      edx, r15d
+       or       edx, r14d
+       and      edx, r12d
+       or       eax, edx
+       add      eax, r13d
+       mov      edx, dword ptr [rbp-0x60]
+       lea      r13d, [rax+rdx+D1FFAB1EH]
+       rol      r13d, 9
+       mov      eax, r12d
+       and      eax, r15d
+       mov      edx, r12d
+						;; size=271 bbWeight=1 PerfScore 32.50
+G_M35977_IG07:
+       or       edx, r15d
+       and      edx, r13d
+       or       eax, edx
+       add      eax, r14d
+       lea      r14d, [rax+r9+D1FFAB1EH]
+       rol      r14d, 13
+       mov      eax, r14d
+       xor      eax, r13d
+       xor      eax, r12d
+       add      eax, r15d
+       mov      edx, dword ptr [rbp-0x64]
+       lea      r15d, [rax+rdx+D1FFAB1EH]
+       rol      r15d, 3
        mov      eax, r15d
        xor      eax, r14d
-       xor      eax, r12d
+       xor      eax, r13d
+       add      eax, r12d
+       lea      r12d, [rax+rsi+D1FFAB1EH]
+       rol      r12d, 9
+       mov      eax, r12d
+       xor      eax, r15d
+       xor      eax, r14d
        add      eax, r13d
-       lea      r13d, [rax+r9+D1FFAB1EH]
-       rol      r13d, 15
-       add      dword ptr [rbx], r12d
+       lea      r13d, [rax+r8+D1FFAB1EH]
+       rol      r13d, 11
+       mov      eax, r13d
+       xor      eax, r12d
+       xor      eax, r15d
+       add      eax, r14d
+       lea      r14d, [rax+rdi+D1FFAB1EH]
+       rol      r14d, 15
+       mov      eax, r14d
+       xor      eax, r13d
+       xor      eax, r12d
+       add      eax, r15d
+       mov      edx, dword ptr [rbp-0x4C]
+       lea      r15d, [rax+rdx+D1FFAB1EH]
+       rol      r15d, 3
+       mov      eax, r15d
+       xor      eax, r14d
+       xor      eax, r13d
+       add      eax, r12d
+       mov      edx, dword ptr [rbp-0x54]
+       lea      r12d, [rax+rdx+D1FFAB1EH]
+       rol      r12d, 9
+       mov      eax, r12d
+       xor      eax, r15d
+       xor      eax, r14d
+       add      eax, r13d
+       mov      edx, dword ptr [rbp-0x50]
+       lea      r13d, [rax+rdx+D1FFAB1EH]
+       rol      r13d, 11
+       mov      eax, r13d
+       xor      eax, r12d
+       xor      eax, r15d
+       add      eax, r14d
+       lea      r14d, [rax+r11+D1FFAB1EH]
+       rol      r14d, 15
+       mov      eax, r14d
+       xor      eax, r13d
+       xor      eax, r12d
+       add      eax, r15d
+       lea      r15d, [rax+rcx+D1FFAB1EH]
+       rol      r15d, 3
+       mov      eax, r15d
+       xor      eax, r14d
+       xor      eax, r13d
+       add      eax, r12d
+       mov      edx, dword ptr [rbp-0x44]
+       lea      r12d, [rax+rdx+D1FFAB1EH]
+       rol      r12d, 9
+       mov      eax, r12d
+       xor      eax, r15d
+       xor      eax, r14d
+       add      eax, r13d
+						;; size=290 bbWeight=1 PerfScore 33.50
+G_M35977_IG08:
+       lea      r13d, [rax+r10+D1FFAB1EH]
+       rol      r13d, 11
+       mov      eax, r13d
+       xor      eax, r12d
+       xor      eax, r15d
+       add      eax, r14d
+       mov      edx, dword ptr [rbp-0x48]
+       lea      r14d, [rax+rdx+D1FFAB1EH]
+       rol      r14d, 15
+       mov      eax, r14d
+       xor      eax, r13d
+       xor      eax, r12d
+       add      eax, r15d
+       mov      edx, dword ptr [rbp-0x58]
+       lea      r15d, [rax+rdx+D1FFAB1EH]
+       rol      r15d, 3
+       mov      eax, r15d
+       xor      eax, r14d
+       xor      eax, r13d
+       add      eax, r12d
+       mov      edx, dword ptr [rbp-0x60]
+       lea      r12d, [rax+rdx+D1FFAB1EH]
+       rol      r12d, 9
+       mov      eax, r12d
+       xor      eax, r15d
+       xor      eax, r14d
+       add      eax, r13d
+       mov      edx, dword ptr [rbp-0x5C]
+       lea      r13d, [rax+rdx+D1FFAB1EH]
+       rol      r13d, 11
+       mov      eax, r13d
+       xor      eax, r12d
+       xor      eax, r15d
+       add      eax, r14d
+       lea      r14d, [rax+r9+D1FFAB1EH]
+       rol      r14d, 15
+       add      dword ptr [rbx], r15d
        lea      r9, bword ptr [rbx+0x04]
-						;; size=287 bbWeight=1 PerfScore 38.00
-G_M35977_IG09:
-       add      dword ptr [r9], r13d
+       add      dword ptr [r9], r14d
        lea      r9, bword ptr [rbx+0x08]
-       add      dword ptr [r9], r15d
+       add      dword ptr [r9], r13d
        add      rbx, 12
-       add      dword ptr [rbx], r14d
+       add      dword ptr [rbx], r12d
        mov      r9, 0xD1FFAB1E
        cmp      qword ptr [rbp-0x30], r9
-       je       SHORT G_M35977_IG10
+       je       SHORT G_M35977_IG09
        call     CORINFO_HELP_FAIL_FAST
-						;; size=38 bbWeight=1 PerfScore 13.00
-G_M35977_IG10:
+						;; size=189 bbWeight=1 PerfScore 34.50
+G_M35977_IG09:
        nop      
 						;; size=1 bbWeight=1 PerfScore 0.25
-G_M35977_IG11:
+G_M35977_IG10:
        lea      rsp, [rbp-0x28]
        pop      rbx
        pop      r12
        pop      r13
        pop      r14
        pop      r15
        pop      rbp
        ret      
 						;; size=15 bbWeight=1 PerfScore 4.50
-G_M35977_IG12:
+G_M35977_IG11:
        test     esi, esi
-       je       SHORT G_M35977_IG13
+       je       SHORT G_M35977_IG12
        mov      r15d, dword ptr [rbx]
        cmp      esi, 1
-       jbe      SHORT G_M35977_IG13
+       jbe      SHORT G_M35977_IG12
        mov      r14d, dword ptr [rbx+0x04]
        cmp      esi, 2
-       jbe      SHORT G_M35977_IG13
+       jbe      SHORT G_M35977_IG12
        mov      r13d, dword ptr [rbx+0x08]
        cmp      esi, 3
-       jbe      SHORT G_M35977_IG13
+       jbe      SHORT G_M35977_IG12
        mov      r12d, dword ptr [rbx+0x0C]
        jmp      G_M35977_IG03
 						;; size=39 bbWeight=0 PerfScore 0.00
-G_M35977_IG13:
+G_M35977_IG12:
        call     CORINFO_HELP_RNGCHKFAIL
        int3     
 						;; size=6 bbWeight=0 PerfScore 0.00
 
-; Total bytes of code 1833, prolog size 39, PerfScore 281.50, instruction count 476, allocated bytes for code 1833 (MethodHash=2e077376) for method System.Net.Security.MD4:MD4Transform(System.Span`1[uint],System.ReadOnlySpan`1[byte]) (FullOpts)
+; Total bytes of code 1648, prolog size 33, PerfScore 242.25, instruction count 458, allocated bytes for code 1648 (MethodHash=2e077376) for method System.Net.Security.MD4:MD4Transform(System.Span`1[uint],System.ReadOnlySpan`1[byte]) (FullOpts)
 ; ============================================================

    Note: some changes were skipped as they were too large to fit into a comment.

    Larger list of diffs: https://gist.github.com/MihuBot/b5906f0767837eff36ac269585bd550d

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