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Remove redundant load that is immediately after the store in same src/dst #35613

Description

@kunalspathak

I have seen below pattern in generated code for framework libraries. We can eliminate the ldr if it is loading the value into same register that was used to store in previous instruction in same memory location.

Example of ARM64 code:

B90023A0          str     w0, [fp,#32]	// [V04 loc1]
B94023A0          ldr     w0, [fp,#32]	// [V04 loc1]

Example of x64 code:

48894C2430           mov      gword ptr [rsp+30H], rcx
488B4C2430           mov      rcx, gword ptr [rsp+30H]

There are approx. 2500 such patterns in 1500 methods. Details in str-ldr.txt.

category:cq
theme:basic-cq
skill-level:intermediate
cost:medium

Activity

  1. changed the title [-]Remove redundant load that is followed by store[/-] [+]Remove redundant load that is immediately after the store in same src/dst[/+] on Apr 29, 2020
  2. added this to the Future milestone on May 3, 2020
  3. removed
    untriagedNew issue has not been triaged by the area owner
    on May 3, 2020
  4. BruceForstall commented on May 3, 2020

    @BruceForstall
    Contributor

    Related: #35614

  5. kunalspathak commented on Jul 14, 2020

    @kunalspathak
    ContributorAuthor

    It turns out that we shouldn't do this optimization for 4-byte registers. Consider for below example, the 2nd instruction zero-extends the upper bits of x0 by doing ldr. If 2nd instruction is eliminated, that won't be true and hence would cause functional bug.

    B90023A0          str     w0, [fp,#32]	// [V04 loc1]
    B94023A0          ldr     w0, [fp,#32]	// [V04 loc1]

    With that, I re-calculated the patterns in framework libraries and looks like there are 1442 patterns in 830 methods.

    Details:
    str-ldr-x.txt

  6. ghost locked as resolved and limited conversation to collaborators on Dec 9, 2020
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    area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMIoptimization

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