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R2R: Cache target of indirect cell address to optimize redundant cell address loading #38890
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Note that the contents of the indirection cell is not invariant. In the example here the second time the call happens the indirection cell will be pointing to the R2R code address and later to tier-1 code, while the first time around it might be pointing to an import thunk.
With that said it might still be ok to do this optimization as the import thunk/delay load helper should be idempotent so calling it a second time in rare cases should be ok (though with loops we should consider avoiding it).
Reacted by Egor BogatovTogether with @jakobbotsch we've just checked that it seems that we already do the right thing here, e.g.:
The address is hoisted, the
ldris not (as expected)- ghost locked as resolved and limited conversation to collaborators
on Aug 19, 2023
Today we don't CSE loading the target of indirect cell address because during CSE we don't have that information in the IR. It happens in later phase like lower.
Consider the following code pattern:
If we can optimize it using peephole or more some ambitious final instructions scanner phase to something like this to:
With this, we can get an improvement of 8 bytes + 1 elimination of memory access.
I wrote an analyzer asm to find out how many addresses are CSE candidates and the number is huge. From what I noticed, it would by little over 2MB of size reduction.
Processed 191816 methods. Found 29246 methods containing 259123 groups.Details: cse-candidates.txt
category:cq
theme:cse
skill-level:expert
cost:large
impact:large