Chisel (@chisel

Pinned

Feb 27, 2020

Videos are up from the Third #ChiselLang Community Conference (presented by @CHIPSAlliance)! See: youtube.com/playlist?list=… Note: there are audio issues with four videos and those will be posted once audio is re-recorded.

youtube.com

CCC 2020

Video recordings from the Third Chisel Community Conference 2020, presented by CHIPS Alliance.

The Chisel Community Conference 2022 in Shanghai (CCC22) starts in 45 minutes at 9 am China Standard Time, 6 pm Pacific! Zoom link is on the Chisel Github!

GitHub - chipsalliance/chisel: Chisel: A Modern Hardware Design Language

Thanks to two first-time contributors to the Chisel and FIRRTL projects: ChiselEnum documentation is dramatically better (github.com/chipsalliance/…) and inline memory initialization in Verilog is now an option (github.com/chipsalliance/…). Nice work by chrisbaldwin2 and @carlosedp. 🙏

Adding ChiselEnum Documentation Entry by chrisbaldwin2 · Pull Request #1795 · chipsalliance/chisel

Chisel 3.4.0 is out! 🎆 Thanks to all the developers who made this release possible.

Jack

@jackakattack

Oct 7, 2020

Chisel v3.4.0 has been released! See the release notes here: github.com/freechipsproje… and try it out on Scastie! scastie.scala-lang.org/LLVNOk9uTDusLj…

Chisel

@chisel_lang

Jul 30, 2020

One more Chisel 3.4.0 feature preview: way better signal naming! (Through a lot of work by @jackakattack and @AdamIzraelevitz.) Full details in @jackakattack's thread. 👇

Jack

@jackakattack

Jul 30, 2020

Very excited to have github.com/freechipsproje… merged to @chisel_lang. As a #Scala library, there was only so much Chisel could do to name signals. In the next major release (3.4), Chisel will provide a compiler plugin to introspect user code and provide much better signal naming.

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