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ARM64: Optimize pair of "ldr reg, [fp]" to ldp #35130
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Related: #35132
I noticed a few things from the attached file:
- Sometimes the low offset comes first, sometimes it comes second in the instruction stream. A peep would need to handle both cases.
- There are a few cases in the attached examples of non-contiguous loads that wouldn't be mergeable (e.g.,
[fp,#72]/[fp,#32]) - Were there any cases of consecutive loads of the
wsub-registers? Or the floating-point registers?
Extending this to arm32, we could use
STMwith a register mask to collapse multiple store (if the consecutive stores were using increasing register numbers, and possibly other conditions were met).- added a commit that references this issue
on Jan 12, 2023 - added a commit that references this issue
on Jan 27, 2023 Fixed in various peepholes, latest being #85032.
- ghost locked as resolved and limited conversation to collaborators
on May 27, 2023
can be combined into
ldpif the loads are happening from subsequent memory.I collected no. of such
ldrpairs in framework libraries and found approx. 28K pairs in 13K methods.Details:
ldr_ldr_fp_to_ldp.txt
category:cq
theme:optimization
skill-level:intermediate
cost:small
impact:medium