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ARM64: Optimize redundant memory loads with mov #35141

Description

@kunalspathak
ldr     w1, [fp,#28]
ldr     w0, [fp,#28]

The 2nd load can be converted into mov which takes 2 fewer cycles than ldr.

ldr     w1, [fp,#28]
mov     w0, w1

I collected no. of such ldr pairs in framework libraries and found approx. 540 pairs in 300 methods.

Details:

ldr_to_mov.txt

category:cq
theme:optimization
skill-level:intermediate
cost:small

Activity

  1. Dotnet-GitSync-Bot commented on Apr 17, 2020

    @Dotnet-GitSync-Bot
    Collaborator

    I couldn't figure out the best area label to add to this issue. Please help me learn by adding exactly one area label.

  2. added this to the Future milestone on Apr 20, 2020
  3. removed
    untriagedNew issue has not been triaged by the area owner
    on Apr 20, 2020
  4. modified the milestones: Future, 6.0.0 on Nov 9, 2020
  5. modified the milestones: 6.0.0, Future on Mar 23, 2021
  6. EgorBo commented on Oct 15, 2021

    @EgorBo
    Member

    NOTE: this opt should not be done for loads of "volatile" fields

  7. ghost added
    in-prThere is an active PR which will close this issue when it is merged
    on Mar 15, 2023
  8. modified the milestones: Future, 8.0.0 on Mar 15, 2023
  9. ghost removed
    in-prThere is an active PR which will close this issue when it is merged
    on Mar 21, 2023
  10. ghost locked as resolved and limited conversation to collaborators on Apr 20, 2023
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    arch-arm64area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMImemory modelissues associated with memory model

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