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[JIT][arm64] CSE for VSD calls #60025

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Description

@EgorBo
void Test(IDisposable d) => d.Dispose();

Currently emits:

; Method Program:Test(System.IDisposable):this
G_M50981_IG01:              ;; offset=0000H
        A9BF7BFD          stp     fp, lr, [sp,#-16]!
        910003FD          mov     fp, sp
						;; bbWeight=1    PerfScore 1.50

G_M50981_IG02:              ;; offset=0008H
        AA0103E0          mov     x0, x1
        D280080B          movz    x11, #64
        F2B9BB8B          movk    x11, #0xcddc LSL #16
        F2CFFFAB          movk    x11, #0x7ffd LSL #32
        D2800801          movz    x1, #64
        F2B9BB81          movk    x1, #0xcddc LSL #16
        F2CFFFA1          movk    x1, #0x7ffd LSL #32
        F9400021          ldr     x1, [x1]
						;; bbWeight=1    PerfScore 6.50

G_M50981_IG03:              ;; offset=0028H
        A8C17BFD          ldp     fp, lr, [sp],#16
        D61F0020          br      x1
						;; bbWeight=1    PerfScore 2.00
; Total bytes of code: 48

Expected codegen:

; Method Program:Test(System.IDisposable):this
G_M50981_IG01:              ;; offset=0000H
        A9BF7BFD          stp     fp, lr, [sp,#-16]!
        910003FD          mov     fp, sp
						;; bbWeight=1    PerfScore 1.50

G_M50981_IG02:              ;; offset=0008H
        AA0103E0          mov     x0, x1
        D2800801          movz    x1, #64
        F2B9BB81          movk    x1, #0xcddc LSL #16
        F2CFFFA1          movk    x1, #0x7ffd LSL #32
        F9400021          ldr     x1, [x1]
						;; bbWeight=1    PerfScore 6.50

G_M50981_IG03:              ;; offset=0028H
        A8C17BFD          ldp     fp, lr, [sp],#16
        D61F0020          br      x1
						;; bbWeight=1    PerfScore 2.00

/cc @dotnet/jit-contrib

Activity

  1. ghost added
    area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
    on Oct 5, 2021
  2. ghost added
    untriagedNew issue has not been triaged by the area owner
    on Oct 5, 2021
  3. removed
    untriagedNew issue has not been triaged by the area owner
    on Oct 5, 2021
  4. added this to the 7.0.0 milestone on Oct 5, 2021
  5. AndyAyersMS commented on Oct 5, 2021

    @AndyAyersMS
    Member

    You mean instead of those composed immediates? I don't think there's much we can do on that front.

    We should however do a better job of CSEing these, or (if this happens in say lower) be smarter about not gratuitously duplicating handle nodes.

            D280080B          movz    x11, #64
            F2B9BBEB          movk    x11, #0xcddf LSL #16
            F2CFFFAB          movk    x11, #0x7ffd LSL #32
            D2800801          movz    x1, #64
            F2B9BBE1          movk    x1, #0xcddf LSL #16
            F2CFFFA1          movk    x1, #0x7ffd LSL #32
  6. EgorBo commented on Oct 5, 2021

    @EgorBo
    MemberAuthor

    You mean instead of those composed immediates? I don't think there's much we can do on that front.

    We should however do a better job of CSEing these, or (if this happens in say lower) be smarter about not gratuitously duplicating handle nodes.

            D280080B          movz    x11, #64
            F2B9BBEB          movk    x11, #0xcddf LSL #16
            F2CFFFAB          movk    x11, #0x7ffd LSL #32
            D2800801          movz    x1, #64
            F2B9BBE1          movk    x1, #0xcddf LSL #16
            F2CFFFA1          movk    x1, #0x7ffd LSL #32

    good point, but looks like the second constant appears in lowering after CSE (#47808 related?)

  7. AndyAyersMS commented on Oct 5, 2021

    @AndyAyersMS
    Member

    Similar -- #47808 was for virtual calls. This is an interface call (VSD).

    We could try to expose this earlier too, and give CSE a chance to work, but it might also be fairly easy to fix in lowering itself as we have to load the thing in a register anyways.

  8. EgorBo commented on Oct 5, 2021

    @EgorBo
    MemberAuthor

    @AndyAyersMS regarding the relocs - I was thinking of a dedicated reg always pointing to the start of a separated heap for Type objects (and string literals) so we could always use relative addressing for those - but it's just thinking out loud

  9. changed the title [-][JIT][arm64] relocs for isinst and VSD[/-] [+][JIT][arm64] CSE for VSD calls[/+] on Oct 5, 2021
  10. AndyAyersMS commented on Oct 5, 2021

    @AndyAyersMS
    Member

    Related Shared constant CSEs should get you something similar, right? Just that the "base" address would be selected based on the actual constants that appear in the IR.

    Right now we allow a limited form of this, perhaps we should expand it?

  11. jakobbotsch commented on Oct 5, 2021

    @jakobbotsch
    Member

    We already do the optimization but it's turned off for tailcalls. I have #59602 that fixes it.

  12. self-assigned this
    on Oct 5, 2021
  13. jakobbotsch commented on Oct 8, 2021

    @jakobbotsch
    Member

    This was actually fixed with #56669.

  14. linked a pull request that will close this issueSupport fast tailcalls in R2R #56669on Oct 8, 2021
  15. ghost locked as resolved and limited conversation to collaborators on Nov 7, 2021
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