[SYCL] Added a new category for device binary properties - #3072

…(#227627)

CodeGenPrepare::splitLargeGEPOffsets collects GEP candidates with large
constant offsets and rebases them to a shared common base, but only for
positive offsets (`ConstantOffset > 0`). Negative far-offset accesses
are left with independent `SUBXri` base materializations per access,
giving them different base registers and preventing the
`LoadStoreOptimizer` from pairing them into `LDP/STP`.

Relax the gate to `ConstantOffset != 0`, and extend
`AArch64TargetLowering::getPreferredLargeGEPBaseOffset` to handle
negative offsets using the same `HighPart = MinOffset & ~0xfff` rebase
as positive ones. For negative `MinOffset`, `HighPart` is the next lower
4096-aligned address, so all residuals (`Offset - HighPart`) are
non-negative and fit `LDR/STR`'s 12-bit unsigned scaled immediate. When
the residual also falls within `LDP/STP`'s 7-bit pairing range, `LSO`
pairs directly; otherwise `LSO`'s base-adjust (#223684) folds in an
extra `ADDXri` (or merges it into a preceding `SUBXri`/`ADDXri` when
adjacent), recovering the same instruction count as a direct rebase to
`MinOffset`.

This subsumes the MIR-level `shareBaseAddresses` pass (#223682) for the
negative-offset case, doing the equivalent work earlier at IR level. It
also benefits cases where LDP pairing isn't possible (non-adjacent
siblings) — the shared base alone saves instructions via CSE, which a
per-BB MIR-level pass can't do.

Example (from https://godbolt.org/z/sjo8eMW6j, 3 non-adjacent
negative-offset siblings, no LDP pairing):
; Before (upstream/main):
mov x8, #-4
mov x9, #-64
mov x10, #-1024
movk x8, #65531, lsl #16
movk x9, #65531, lsl #16
movk x10, #65531, lsl #16
ldr w8, x0, x8
ldr w9, x0, x9
ldr w10, x0, x10
; 9 instructions

; After (this patch):
sub x8, x0, #65, lsl #12   ; =266240
ldr w9, [x8, #4092]
ldr w10, [x8, #4032]
ldr w8, [x8, #3072]
; 4 instructions vs 9

Testing:
- Full AArch64 CodeGen test suite with assertions enabled (4301 tests, 0
regressions; 2 pre-existing upstream failures in
`arm64-codegen-prepare-extload.ll` and `and-sink.ll`, unrelated to this
change)
- `llvm-test-suite` (3535 passed, 0 failures, 0 errors)
- Bootstrap: building the entire LLVM+Clang with the patched clang
(assertions on, no crashes)

Note: `AArch64` is the only target that overrides
`shouldConsiderGEPOffsetSplit` and `getPreferredLargeGEPBaseOffset`, so
the gate change only affects AArch64 in practice.

Assisted-by: Claude (OpenCode)