Skip to content

stm32/qspi.c: Allow qspi_write_cmd_data to write cmd with 1 data byte. - #11931

Merged
dpgeorge merged 1 commit into
micropython:masterfrom
victorallume:feature/allow_single_databyte_qspi_write_cmd_data
Jul 13, 2023
Merged

dpgeorge merged 1 commit into
micropython:masterfrom
victorallume:feature/allow_single_databyte_qspi_write_cmd_data

Conversation

@victorallume

Copy link
Copy Markdown
Contributor

The existing qspi for stm32 implementation can only send a spi command with exactly 0 or 2 data bytes. Certain spiflash chips (e.g. AT25SF321B) have commands that only take a single data byte, and will ignore the command if more than that is sent. This allows sending a command with a single data byte. Would be nicer to have a general function to send n bytes, but there probably aren't many commands that require this.

@victorallume
victorallume force-pushed the feature/allow_single_databyte_qspi_write_cmd_data branch 2 times, most recently from 6ce2eb9 to 59824a6 Compare July 4, 2023 05:36
@victorallume victorallume changed the title allow qspi_write_cmd_data to write a cmd with 1 byte of data stm32/qspi.c: Allow qspi_write_cmd_data to write cmd with 1 data byte. Jul 4, 2023
@victorallume
victorallume force-pushed the feature/allow_single_databyte_qspi_write_cmd_data branch from 59824a6 to 62760e0 Compare July 4, 2023 05:56
victorallume added a commit to victorallume/micropython that referenced this pull request Jul 4, 2023
The existing spiflash driver writes both bytes of SR as a single command.
Some flash chips don't support multi-byte writes such as this, and have a
seperate command to write SR byte 1 and SR byte 2 (referred to in the code
as CR). This used in the spiflash initialisation to enable quad mode. The
quad enable bit is in the second SR byte. This change still issues the
multi-byte command, then issues a single byte command for just the second
SR byte. For chips that only support one of the commands, the unsupported
command should be ignored silently. For chips that support both types of
command, the SR will be written twice.

This depends on micropython#11931 for
the stm32 port to allow single-byte spi commands.

Signed-off-by: Victor Rajewski <[email protected]>
victorallume added a commit to victorallume/micropython that referenced this pull request Jul 4, 2023
The existing spiflash driver writes both bytes of SR as a single command.
Some flash chips don't support multi-byte writes such as this, and have a
seperate command to write SR byte 1 and SR byte 2 (referred to in the code
as CR). This used in the spiflash initialisation to enable quad mode. The
quad enable bit is in the second SR byte. This change still issues the
multi-byte command, then issues a single byte command for just the second
SR byte. For chips that only support one of the commands, the unsupported
command should be ignored silently. For chips that support both types of
command, the SR will be written twice.

This depends on micropython#11931 for
the stm32 port to allow single-byte spi commands.

Signed-off-by: Victor Rajewski <[email protected]>
The existing qspi for stm32 implementation can only send a spi command with
exactly 0 or 2 data bytes.  Certain spiflash chips (e.g. AT25SF321B) have
commands that only take a single data byte, and will ignore the command if
more than that is sent.  This commit allows sending a command with a single
data byte.

Signed-off-by: Victor Rajewski <[email protected]>
@dpgeorge
dpgeorge force-pushed the feature/allow_single_databyte_qspi_write_cmd_data branch from 62760e0 to 730525c Compare July 13, 2023 02:51
@dpgeorge
dpgeorge merged commit 730525c into micropython:master Jul 13, 2023
@dpgeorge

Copy link
Copy Markdown
Member

Thanks for this, it looks correct.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Projects

None yet

Development

Successfully merging this pull request may close these issues.

2 participants