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[SYCL] span for SYCL2020 support - #3569
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SYCL2020 spec adds span to the sycl namespace, even when not compiling C++20. I have adapted the Clang libcxx version of span here, divorcing it from its macros and private access to implementation details, but otherwise mostly intact. Signed-off-by: Chris Perkins <[email protected]>
Signed-off-by: Chris Perkins <[email protected]>
Signed-off-by: Chris Perkins <[email protected]>
Signed-off-by: Chris Perkins <[email protected]>
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I'm converting this to draft while I investigate the Win building issue. It builds ,runs and tests fine for me on Windows. What version of MSVC are we using on the CI system? I wonder if that is the difference? |
You can see that on configuration step: |
Signed-off-by: Chris Perkins <[email protected]>
Signed-off-by: Chris Perkins <[email protected]>
Signed-off-by: Chris Perkins <[email protected]>
Signed-off-by: Chris Perkins <[email protected]>
| usm_span[0] += 100; // 101 modify first value using span affordance. | ||
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| event E = Q.submit([&](handler &cgh) { | ||
| auto can_read_from_span_acc = SpanRead.get_access<access::mode::write>(cgh); |
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Mind boggling this can_read with a mode::write :-)
I think the root cause is the buffer named SpanRead.
Just naming it buf or whatever would not cause all these semantic clashes...
Same for other accessors and buffers.
Use comments instead, if things need to be clarified.
Signed-off-by: Chris Perkins <[email protected]>
Signed-off-by: Chris Perkins <[email protected]>
Signed-off-by: Chris Perkins <[email protected]>
Signed-off-by: Chris Perkins <[email protected]>
Signed-off-by: Chris Perkins <[email protected]>
Signed-off-by: Chris Perkins <[email protected]>
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pinging codeowners |
* upstream/sycl: [SYCL][Doc] Add group sorting algorithms extension specification (intel#3514) [Buildbot] Update Windows GPU driver to 27.20.100.9466 (intel#3594) [SYCL][NFC] Update tests for FPGA attributes (intel#3632) [CODEOWNERS] Add @kbobrovs back to few projects (intel#3638) [NFC] Update codeowners (intel#3619) [SYCL] Support 3-, 16-elements vectors in SG load/store (intel#3617) [SYCL-PTX] Fix libclc dependencies (intel#3624) [SYCL] Add sycl::span for SYCL2020 support (intel#3569) [NFC][SYCL] Avoid -Wreorder warning about order of initialization (intel#3620) [SYCL][DOC] Initial Draft of Extension for querying free device memory on Level Zero (intel#3468) [SYCL][PI][L0] Submit open command batch on event status query (intel#3612) [NFC] Fix the comment (intel#3613) Rename misleading attribute flag (intel#3610) [SYCL] Generate an opt report of kernel arguments. (intel#3492) [SYCL] Support extra environment variables in LIT (intel#3598) [SYCL][Matrix] Make joint_matrix_mad return A*B+C's result instead of C=A*B+C (intel#3586)
Disable SPIR-V validation in some tests that do not pass with current
HEAD of SPIRV-Tools (cb38b234 ("spirv-opt: Add LegalizeMultidim...",
2026-02-11)) while the discussion of #3569 is ongoing.
Original commit:
KhronosGroup/SPIRV-LLVM-Translator@8189551551d2bdb
Disable SPIR-V validation in some tests that do not pass with current
HEAD of SPIRV-Tools (cb38b234 ("spirv-opt: Add LegalizeMultidim...",
2026-02-11)) while the discussion of #3569 is ongoing.
Original commit:
KhronosGroup/SPIRV-LLVM-Translator@8189551551d2bdb
…nsics (intel#3771) Fixes misuse of `FPRoundingMode` on some unsupported intrinsics which violates the OpenCL SPIR-V spec: https://registry.khronos.org/OpenCL/specs/unified/html/OpenCL_Env.html#_rounding_modes_for_conversions Such misuse can now be detected by `spirv-val`. Mirrors the [same fix](llvm/llvm-project#182742) in the SPIR-V backend in LLVM. Resolves intel#3569 Original commit: KhronosGroup/SPIRV-LLVM-Translator@148a0b9560a8dcc
SYCL2020 introduces
spaninto the SYCL namespace, even when not compiling with C++20. I have adapted the Clang libcxx version of span here, divorcing it from its macros and private access to implementation details, but otherwise mostly intact.